CTSEN=DISABLED, CTS=LOW, UCLK=LOW, RTSTH=FULL, TIRDAPW=1_16TH, TX=LOW, RTSEN=DISABLED, RX=LOW, RTS=LOW, CTSINVEN=DISABLED, RTSINVEN=DISABLED
Flow Control
| RTS | RTS State. 0 (LOW): RTS pin (before optional inversion) is driven low. 1 (HIGH): RTS pin (before optional inversion) is driven high. |
| RX | RX Pin Status. 0 (LOW): RX pin (after optional inversion) is low. 1 (HIGH): RX pin (after optional inversion) is high. |
| RTSINVEN | RTS Invert Enable. 0 (DISABLED): The USART does not invert the RTS signal before driving the pin. 1 (ENABLED): The USART inverts the RTS signal driving the pin. |
| RTSTH | RTS Threshold Control. 0 (FULL): RTS is de-asserted when the receive FIFO and shift register are full and no more incoming data can be stored. 1 (ONE_BYTE_FREE): RTS is de-asserted when the receive FIFO and shift register are nearly full and only one more data can be received. |
| RTSEN | RTS Enable. 0 (DISABLED): The RTS state is not changed by hardware. The RTS bit can be written only when hardware RTS is disabled (RTSEN = 0). 1 (ENABLED): Hardware sets RTS when the receive FIFO is at or above the threshold set by RTSTH and clears RTS otherwise. |
| CTS | CTS State. 0 (LOW): Indicates the CTS pin state (after optional inversion) is low. 1 (HIGH): Indicates the CTS pin state (after optional inversion) is high. |
| TX | TX State. 0 (LOW): The TX pin (before optional inversion) is low. 1 (HIGH): The TX pin (before optional inversion) is high. |
| UCLK | UCLK State. 0 (LOW): The UCLK pin is low. 1 (HIGH): The UCLK pin is high. |
| CTSINVEN | CTS Invert Enable. 0 (DISABLED): The USART does not invert CTS. 1 (ENABLED): The USART inverts CTS. |
| CTSEN | CTS Enable. 0 (DISABLED): The CTS pin state does not affect transmissions. 1 (ENABLED): Transmissions will begin only if the CTS pin (after optional inversion) is low. |
| TIRDAPW | Transmit IrDA Pulse Width. 0 (1_16TH): The IrDA pulse width is 1/16th of a bit period. 1 (1_8TH): The IrDA pulse width is 1/8th of a bit period. 2 (3_16TH): The IrDA pulse width is 3/16th of a bit period. 3 (1_4TH): The IrDA pulse width is 1/4th of a bit period. |